Verification →
Compile a test, follow signals through the waveform, catch an injected bug, and inspect coverage.
VCS · Verdi · URG
Terminal + GUI · UW–Madison CAE
Synopsys on CAE
Get from a browser login to a working chip design tool flow. These three guides walk through the same small register example, with real screenshots and commands you can run yourself.
PDF ↓
RTL Development →
Read the hardware contract, simulate changes, and inspect the mapped logic and timing.
SystemVerilog · Verdi · Design Vision
Synthesis and Physical Design →
Constrain and synthesize the example, build its reference library, and inspect a saved floorplan and initial placement.
Design Compiler · Design Vision · ICC2
Start with access
Use your own UW NetID to open CAE Guacamole. Complete the UW web sign-in and then the Linux desktop login. Each guide includes the full access walkthrough, terminal basics, and the Synopsys environment setup.
You need CAE access and its licensed tool environment. The teaching source is public; the tools and libraries stay on CAE. See the official CAE login instructions if you cannot reach the desktop.
One lab, three ways to explore it
Verification follows stimulus and checks through simulation. RTL connects source behavior to mapped hardware. Synthesis and physical design follow constraints, reports, and initial placement. You can work through your guide independently.
This is a one-register teaching exercise. Initial placement is not a completed place-and-route or signoff flow. Its timing and area measurements describe only this example. The validation record lists what was tested and the remaining limits.
Example code
Code: RTL · Testbench · Runner · Synthesis script · Reference library script · Floorplan script
The HTML pages and PDFs use the same manuscripts. Screenshots retain the original demonstration folder; use the paths in the command blocks.